1. Field of the Invention
The present invention relates in general to integrated circuit (IC) manufacturing and, more specifically, to methods in IC manufacturing processes for sorting IC devices using identification (ID) codes, such as fuse IDs, in the devices.
2. State of the Art
Integrated circuits (ICs) are small electronic circuits formed on the surface of a wafer of semiconductor material, such as silicon, in an IC manufacturing process referred to as xe2x80x9cfabrication.xe2x80x9d Once fabricated, ICs are electronically probed to evaluate a variety of their electronic characteristics, cut from the wafer on which they were formed into discrete IC dice or xe2x80x9cchips,xe2x80x9d and then assembled for customer use using various well-known IC packaging techniques, including lead frame packaging, Chip-On-Board (COB) packaging, and flip-chip packaging.
Before being shipped to customers, packaged ICs are generally tested to ensure they will function properly once shipped. Testing typically involves a variety of known test steps, such as pre-grade, bum-in, and final, which test ICs for defects and functionality and grade ICs for speed. As shown in FIG. 1, ICs that pass the described testing are generally shipped to customers, while ICs that fail the testing are typically rejected.
The testing standards for a particular IC product are sometimes relaxed as the product xe2x80x9cmaturesxe2x80x9d such that ICs previously rejected under strict testing standards may pass the relaxed testing standards. Consequently, reject bins containing previously rejected ICs are sometimes xe2x80x9cculledxe2x80x9d for ICs that are shippable under relaxed testing standards by testing the rejected ICs again using the relaxed testing standards. Unfortunately, while this xe2x80x9ccullingxe2x80x9d process does retrieve shippable ICs from reject bins, it makes inefficient use of expensive and often limited testing resources by diverting those resources away from testing untested ICs in order to retest previously rejected ICs. Therefore, there is a need in the art for an improved method of xe2x80x9ccullingxe2x80x9d or sorting such reject bins for shippable ICs.
Similarly, as shown in FIG. 2, all the ICs from the wafers in a wafer lot typically undergo enhanced reliability testing that is more extensive and strict than normal testing when any of the wafers in the lot are deemed to be unreliable because of fabrication or other process errors. Since a wafer lot typically consists of fifty or more wafers, many of the ICs that undergo the enhanced reliability testing do not require it because they come from wafers that are not deemed unreliable. Performing enhanced reliability testing on ICs that do not need it is inefficient because such testing is typically more time-consuming and uses more resources than normal testing. Therefore, there is a need in the art for a method of sorting ICs from a wafer lot into those ICs that require enhanced reliability testing and those that do not.
Likewise, as shown in FIG. 3, a new or special xe2x80x9crecipexe2x80x9d for fabricating ICs on wafers is sometimes tested by fabricating some wafers from a wafer lot using the special recipe and other wafers from the wafer lot using a control recipe. ICs from the wafers then typically undergo separate assembly and test procedures so that the test results of ICs fabricated using the special recipe are not mixed with the test results of ICs fabricated using the control recipe, and vice versa. Test reports from the separate test procedures are then used to evaluate the special recipe and to determine whether the ICs are to be shipped to customers, reworked, repaired, retested, or rejected. Unfortunately, because the ICs undergo separate test and assembly procedures, undesirable variables, such as differences in assembly and test equipment, are introduced into the testing of the special recipe. It would be desirable, instead, to be able to assemble and test the ICs using the same assembly and test procedures, and to then sort the ICs and their test results into those ICs fabricated using the special recipe and those ICs fabricated using the control recipe. Therefore, there is a need in the art for a method of identifying individual ICs fabricated using a special or control recipe and sorting the ICs based on their fabrication recipe.
As described above, ICs are typically tested for various characteristics before being shipped to customers. For example, as shown in FIG. 4, ICs may be graded in test for speed and placed in various bins (e.g., 5 nanoseconds (ns), 6 ns, and 7 ns bins) according to their grading. If a customer subsequently requests a more stringent speed grade (e.g., 4 ns), ICs in one of the bins (e.g., a 5 ns bin) are re-tested and thereby sorted into ICs that meet the more stringent speed grade (e.g., 4 ns bin) and those that do not (e.g., 5 ns bin). While this conventional process sorts the ICs into separate speed grades, it makes inefficient use of expensive and often limited testing resources by diverting those resources away from testing untested ICs in order to retest previously tested ICs. Therefore, there is a need in the art for an improved method of xe2x80x9ccullingxe2x80x9d or sorting bins for ICs that meet more stringent standards, such as a higher speed grading.
As described in U.S. Pat. Nos. 5,301,143, 5,294,812, and 5,103,166, some methods have been devised to electronically identify individual ICs. Such methods take place xe2x80x9coffxe2x80x9d the manufacturing line and involve the use of electrically retrievable ID codes, such as socalled xe2x80x9cfuse IDs,xe2x80x9d programmed into individual ICs to identify the ICs. The programming of a fuse ID typically involves selectively blowing an arrangement of fuses and anti-fuses in an IC so that when the fuses or anti-fuses are accessed, they output a selected ID code. Unfortunately, none of these methods addresses the problem of identifying and sorting ICs xe2x80x9conxe2x80x9d a manufacturing line.
An inventive method for sorting integrated circuit (IC) devices of the type to have a substantially unique identification (ID) code, such as a fuse ID, includes automatically reading the ID code of each of the IC devices and sorting the IC devices according to their automatically read ID codes. The inventive method can be used in conjunction with an IC manufacturing process that includes providing semiconductor wafers, fabricating the ICs on each of the wafers, causing each of the ICs to store its ID code, separating each of the ICs from its wafer to form an IC die, assembling the IC dice into IC devices, and testing the IC devices. The method can also be used in conjunction with Single In-line Memory Module (SIMM), Dual In-line Memory Module (DIMM), and other multi-chip module (MCM) manufacturing processes.
In another embodiment, an inventive method for recovering IC devices from a group of IC devices that have previously been rejected in accordance with a test standard that has since been relaxed includes: storing test results that caused each of the IC devices in the group to be rejected in connection with an ID code, such as a fuse ID, associated with each device; automatically reading the ID code from each of the IC devices; accessing the test results stored in connection with each of the automatically read ID codes; comparing the accessed test results for each of the IC devices with the relaxed test standard; and sorting the IC devices according to whether their accessed test results pass the relaxed test standard in order to recover any of the IC devices having test results that pass the relaxed test standard.
By sorting the IC devices in accordance with their previously stored test results and their ID codes, the above-described inventive method eliminates the need to retest the IC devices after the test standard is relaxed in order to cull shippable IC devices from the rejected devices.
In still another embodiment, a method for sorting a group of IC devices in accordance with a first IC standard, such as a speed standard, that have previously been sorted in accordance with a second IC standard, such as a speed standard, that is less stringent than the first IC standard, includes storing test results that caused each of the IC devices in the group to be sorted into the group in connection with ID codes, such as fuse IDs, of the devices, automatically reading the ID code from each of the IC devices, accessing the test results stored in connection with each of the automatically read ID codes, comparing the accessed test results for each of the IC devices with the first IC standard, and sorting the IC devices according to whether their test results pass the first IC standard.
In a further embodiment, an inventive back-end test method for separating IC devices in need of enhanced reliability testing from a group of IC devices undergoing back-end test procedures includes: storing a flag in connection with an ID code, such as a fuse ID, associated with each of the IC devices in the group indicating whether each IC device is in need of enhanced reliability testing; automatically reading the ID code of each of the IC devices in the group; accessing the enhanced reliability testing flag stored in connection with each of the automatically read ID codes; and sorting the IC devices in accordance with whether their enhanced reliability testing flag indicates they are in need of enhanced reliability testing.
Thus, the inventive method described above provides an advantageous method for sorting ICs from the same wafer lot into those ICs that require enhanced reliability testing and those that do not.
In a still further embodiment, an inventive method in an IC manufacturing process for testing different fabrication process recipes includes the following: providing first and second pluralities of semiconductor wafers; fabricating a first plurality of ICs on each of the first plurality of wafers in accordance with a control recipe; fabricating a second plurality of ICs on each of the second plurality of wafers in accordance with a test recipe; causing each of the ICs on each of the wafers to permanently store a substantially unique ID code, such as a fuse ID; separating each of the ICs on each of the wafers from its wafer to form one of a plurality of IC dice; assembling each of the IC dice into an IC device; automatically reading the ID code from the IC in each of the IC devices; testing each of the IC devices; and sorting each of the IC devices in accordance with the automatically read ID code from the IC in each of the IC devices indicating the IC is from one of the first and second pluralities of ICs.